EDN

VHDL-200x improves design and verification productivity

VHDL is a critical language for RTL design and is a major component of the $200+ million RTL simulation market 1. Many users prefer VHDL for RTL design because the language continues to provide ...
Business Wire

Aldec Brings Assertions to FPGA Designers with the Release of Active-HDL 8.1

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-language simulation for ASIC and FPGA devices, announced today the release of Active-HDL 8.1. The new release introduces a ...
Design-Reuse

XML-Based Assertion Generation

Implementing comprehensive assertions traditionally involves writing complicated temporal expressions and properties using an assertion language or hand-coding tests ...
Design-Reuse

SystemVerilog-VHDL-SystemC Verification IP Reuse Methodology

The growing complexity of SoCs and the reduced life cycle of electronic products demand higher levels of design productivity while meeting compressed development schedules. The reuse of design IP ...