Electronic Design

A Summary Of The DDR Memory Controller Standard—Wait, There Isn’t One!

The number of systems-on-a-chip (SoCs) that require an interface to off-chip memory is increasing. As a result, more and more designers are turning to double-data-rate (DDR) SDRAM interfaces such as ...
Electronic Design

PWM Controller IC Aims At DDR Memory Arrays

The IRU3038 synchronous pulse-width modulation (PWM) controller IC handles the termination-voltage requirements of double-data-rate (DDR) memory arrays. By ...
Ars Technica

Will dual-channel DDR rival or beat Rambus?

This question occured to me whilst perusing a couple of other threads - this one and this one and I figured it might benefit from a post of it's own.<BR><BR>Dual-channel DDR memory controllers offer a ...
EDN

Synopsys Launches Full Range of Silicon-Proven DDR3 and DDR2 IP Solutions for SoC Designs

MOUNTAIN VIEW, Calif., Aug. 13 /PRNewswire-FirstCall/ — Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design and manufacturing ...
EDN

Power controller offers DDR2 SDRAM voltages

Targeting notebooks, tablet PCs, and embedded applications, the SC1486A dual synchronous DDR and DDR2 buck power supply controller offers input voltages from 1.8 to 25 V�enabling the device to ...
Semiconductor Engineering

DDR Memory Test Challenges From DDR3 to DDR5

Cloud, networking, enterprise, high-performance computing, big data, and artificial intelligence are propelling the development of double data rate (DDR) memory chip technology. Demand for lower power ...