The rule of thumb to use a 0.1-µF capacitor on the power pin of a semiconductor device is rapidly fading away. Semiconductor products of today have multiple power pins and voltages. But, it is more ...

You are designing your latest sub-system and somebody tells you to place as many 100 nF decoupling capacitors as you can, as close as physically possible to all the integrated circuits, just like we ...

[Bertho] really enjoyed pawing through the pile of projects submitted to the 7400 logic contest. But one thing kept hitting him with the vast majority of the entries: decoupling capacitors were ...

Decoupling capacitors have long been an important aspect of maintaining a clean power source for integrated circuits, but with noise caused by rising clock frequencies, multiple power domains, and ...

Noise management, induced by digital circuits on a p. c. board assembly, deserves the attention of power supply designers and those mastering digital, analog, and mixed-mode application problems ...

CMOS technology has evolved as the top choice for chip manufacturers. There are multiple reasons for its emergence to its current status, continuous reduction in feature size being one of them. SoC ...

Because of their high ESL compared to ceramic, tantalum capacitors are not the optimum choice for high frequency decoupling. Paralleling tantalum capacitors for bulk capacitance and ceramic for high ...

This white paper discusses a method for driving high-frequency sinusoidal ripple over capacitive loads for power supply rejection ratio (PSRR) testing, an important performance parameter for many ...

Everyone knows that the perfect capacitor to decouple the power rails around ICs is a 100 nF ceramic capacitor or equivalent, yet where does this ‘fact’ come from and is it even correct? These are the ...