Philippe Luc, director of verification at Codasip, talked to students of the UK Electronics Skills Foundation (UKESF) about what it is like to be a verification engineer. On one hand the UKESF ...

Cadence Design Systems stock was climbing as it said its AI agent can now independently carry out complex work on chip design ...

At Computex 2026, Cadence (Nasdaq: CDNS) announced the industry’s first fully autonomous virtual agentic AI design engineer, ...

Semiconductor Engineering sat down to discuss the implications of having an executable specification that drives verification with Hagai Arbel, chief executive officer for VTool; Adnan Hamid, chief ...

Cadence unveiled a Level-5 autonomous AI design engineer powered by NVIDIA technologies, aiming to reduce semiconductor ...

Bringing agentic AI into chip verification to accelerate design cycles, improve verification quality, and increase ...

Groundbreaking benefits of using artificial intelligence in design verification. How SHAPley values can help engineers optimize debugging in design verification. Achieving low-latency SoC ...

Tell us a little about your professional and/or educational background. I did my bachelors’ degree in electrical and electronics in India. After graduating, I worked at Intel for a year as a design ...

Challenges facing chip design verification engineers are plentiful, but the opportunities, especially for AI applications, are abundant Challenges facing chip design verification engineers are ...

As the cost of chip turns has grown from thousands to millions of dollars, missed design bugs are unacceptable Chip design verification used to be straightforward, if not always easy. Verification ...

It’s time to put to rest 11 of the most common myths about verification intellectual property (VIP). SmartDV’s Bipul Talukdar, Director of Applications Engineering, explains why it’s used in a ...