Semiconductor Engineering

Across The Vast Reaches Of The 3D Stack: Mastering ESD Verification In Advanced Semiconductor Design

In the vast reaches of the semiconductor cosmos, a silent menace lurks—one that can obliterate years of design work in a fraction of a nanosecond. Electrostatic discharge (ESD) verification stands as ...
Business Wire

Apache Introduces PathFinder, the Industry’s First Full-chip ESD Physical Integrity Solution

SAN JOSE, Calif.--(BUSINESS WIRE)--Apache Design Solutions, the technology leader in power integrity and noise closure for chip-package-systems (CPS) convergence, today announced PathFinder™, a ...
EDN

ESD Process Shrinks I/Os Along Core Path

IC cores have shrunk significantly with ever-smaller process geometries, but the I/Os have basically been stuck at the same sizes since 0.5-micron CMOS. Now with new compact electrostatic discharge ...
Electronics Weekly

New process cuts die size, I/O and ESD

New process cuts die size, I/O and ESDNews from E-InSiteSarnoff, the company that pioneered CMOS process technology, has unveiled its TakeCharge! technology for IC design, which it claims reduces die ...
Semiconductor Engineering

Verifying Your Intent

Design rule checking (DRC), layout versus schematic (LVS) and electrical rule checking (ERC) are physical verification techniques that are mandatory today to check a design and its structures before ...