Yahoo

STMicroelectronics in Cooperation With Soitec Makes 28nm FD-SOI CMOS Process Available Through CMP

GENEVA and GRENOBLE, FRANCE--(Marketwire - Oct 18, 2012) - STMicroelectronics (NYSE: STM), Soitec (Euronext) and CMP (Circuits Multi Projets®) today announced that ST's CMOS 28nm Fully Depleted ...
Semiconductor Engineering

What’s ST’s FD-SOI Technology All About?

As I blogged here on SemiMD last week, STMicroelectronics has announced that to supplement in-house production at their fab in Crolles, the company has tapped GlobalFoundries for high-volume ...
Electronics Weekly

NANO16: FD-SOI moves towards 22nm and 14nm

Over the next four years, WAYTOGO FAST will work on the most suitable generations of FD-SOI technologies to answer market requirements. At the end of the project (29 months) the pilot line should be ...
Semiconductor Engineering

Considerations for Porting a Bulk CMOS Design to FD-SOI

Technologists describe a straight port of an existing bulk CMOS design to FD-SOI at the same node, obtaining the value of fully depleted SOI for a modest redesign effort. November 16th, 2012 - By: ...
Electronic Design

FD-SOI Perpetuates Moore’s Law

A CMOS 28nm fully depleted silicon-on-insulator (FD-SOI) process devised by STMicroelectronics (using silicon substrates from Soitec) is now available for prototyping to universities, research labs, ...
EDN

SOI Industry Consortium Publishes Technical Paper on Porting Semiconductor Designs From Bulk Silicon to FD-SOI

A group of leading semiconductor companies have developed a roadmap for leveraging CMOS designs intended for manufacturing on bulk silicon to fabricate ICs on fully depleted silicon-on-insulator ...
Electronics Weekly

ST runs cool 3GHz FD-SOI processors

STMicroelectronics is making application processors on its FD-SOI process running at 3GHz with ‘greater power efficiency at a given operating frequency than alternate technologies,’ says the company. ...
Nanowerk

Local-strain techniques in FD-SOI fabrication improve Next-generation performance, energy use

(Nanowerk News) CEA-Leti today announced it has developed two techniques to induce local strain in FD-SOI processes for next-generation FD-SOI circuits that will produce more speed at the same, or ...
Design-Reuse

40 GHz VCO and Frequency Divider in 28 nm FD-SOI CMOS Technology for Automotive Radar Sensors

1 STMicroelectronics, 95121 Catania, Italy; giorgio.maiellaro@st.com (G.M.); giovanni.caruso@st.com (G.C.); salvo.scaccianoce@st.com (S.S.) 2 STMicroelectronics ...
EDN

IC Knowledge’s Cost Modeling of Semiconductor Manufacturing Shows Fully Depleted Silicon-on-Insulator Technology to be the Most Cost-effective Approach at the 22nm Node

Research firm IC Knowledge LLC has completed a comprehensivecost analysis that determines fully depleted silicon-on-insulator(FD-SOI) wafers offer the global semiconductor industry the mostcost ...
Yahoo Finance

VeriSilicon Introduces FD-SOI Wireless IP Platform for Diverse IoT and Consumer Electronics Applications

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New Electronics

CEA and Quobly report microsecond qubit-readout solution with 10x power-use reduction

This has been achieved while reducing the readout power consumption by 10x and footprint by 2x and combined with Quobly’s strategy to build qubits out of FD-SOI technology, this readout architecture ...