RF Globalnet

Altera Introduces Next-Generation Agilex 9 Direct RF-Series SoC FPGA To Power The Future Of High-Performance RF Systems

Altera announced engineering samples of its next-generation Agilex 9 Direct RF-Series SoC FPGAs, delivering 40% greater compute density for aerospace, defense, and communications applications.
Semiconductor Engineering

New Embedded FPGA Compiler Maximizes IP Implementation Efficiency

When designing IP for system-on-chip (SoC) and application-specific integrated circuit (ASIC) implementations, IP designers strive for perfection. Optimal engineering often yields the smallest die ...
Design-Reuse

FPGA Implementation of DLX Microprocessor With WISHBONE SoC Bus

DLX is an open source microprocessor, it’s free and it has never been implemented in a commercial ASIC (Application Specific Integrated Circuit) design. The objective of this project is to use the ...
Electronic Design

Secure FPGA RISC-V SoC Forgoes Heatsink

How a cool FPGA needs so little power. The importance of a smaller RISC-V SoC FPGA. What the PolarFire SoC means to RISC-V developers. Why security and reliability are key to PolarFire’s success. Very ...
Design-Reuse

Understanding FPGAs – From Architecture to SoC, RFSoC, and Embedded FPGA Technologies

One of the most crucial components of modern digital systems, field programmable gate arrays (FPGAs) provide for flexibility, parallel processing, and hardware-level acceleration. FPGAs, in contrast ...
EDN

ARM-based SoC FPGAs

Altera Corporation today unveiled its family of ARM-based SoC FPGAs, integrating 28-nm Cyclone® V and Arria® V FPGA fabric, a dual-core ARM® Cortex™-A9 MPCore ...
Electronic Design

Solutions Mitigate Mixed-Signal SoC Implementation Headaches

The concept of silicon realization, as defined in the Cadence EDA360 vision paper, represents everything required to produce a system-on-a-chip (SoC) design in silicon. 1 Silicon realization addresses ...
Semiconductor Engineering

Adding NoCs To FPGA SoCs

FPGA SoCs straddle the line between flexibility and performance by combining elements of both FPGAs and ASICs. But as they find a home in more safety- and mission-critical markets, they also are ...
EDN

Design planning for large SoC implementation at 40nm: Guaranteeing predictable schedule and first-pass silicon success

The physical design implementation of large complex deep sub-micron technologies has evolved to a stage where it is essential to consider every aspect of SoC design and implementation during the ...