Constrained random test pattern generation entered the scene a couple of decades ago as a better way to spend time and resources for the creation of stimulus. Stimulus definition had become an arduous ...

The huge undertaking of verifying a system-on-chip (SoC) design has challenged engineers for more than 20 years –– the amount of time spent on it hasn’t varied much from between 50-70% of the entire ...

Let’s say you have a block you need to verify. How do you know that the stimulus you are about to use is exhaustive enough and that you have covered the necessary scenarios/situations to prove it is ...

Functional coverage is probably one of the most important components of constrained random verification strategy. Given this fact, it should be written taking every usefulaspect into account such that ...

PARTNER CONTENT: Given the size and complexity of modern semiconductor designs, functional verification has become a dominant phase in the development cycle. Coverage lies at the very heart of this ...

As VLSI designs grow in complexity ranging from multi-core SoCs to AI accelerators verification has become the dominant cost and schedule driver in chip development. Two major verification ...

Chip-verification teams often confront one fundamental question: “How well is the verification process exercising the design?” Attempts to answer this query have led to the development of several ...

If you don’t measure something you certainly can’t improve it in any meaningful way. This is especially important with a process that can never be completed due to the sheer magnitude of the ...