EDN

Layout compaction accelerates SoC design through hard IP reuse

In enabling multimillion-gate SoC designs, the latest process technologies have widened the gap between manufacturing capabilities and designers' abilities to quickly put together these complex ...
Yahoo Finance

GBT Seeks to Develop an AI Empowered Technology for Automatic Compaction of Integrated Circuit Layout Data IPs

SAN DIEGO, Feb. 15, 2022 (GLOBE NEWSWIRE) -- GBT Technologies Inc. (OTC PINK: GTCH ) ("GBT” or the “Company”), is developing an AI empowered technology for automatic compaction of integrated circuit ...
Yahoo Finance

GBT Commences Research and Development of Delta, an Automated IC Layout Process Migration and Compaction Technology

SAN DIEGO, April 15, 2021 (GLOBE NEWSWIRE) -- GBT Technologies Inc. (OTC PINK: GTCH) ("GBT” or the “Company”), started research and development of Delta, a new EDA (Electronic Design Automation) ...
Design-Reuse

Analog IP Reuse in Nano Technologies

Sherif Hammouda, Mentor Graphics Cairo Egypt. Hazem Said, Ain Shams University Cairo Egypt. Mohamed Dessouky, Mentor Graphics Cairo Egypt. Mohamed Tawfik, Mentor Graphics Cairo Egypt. Presented in ...
Mena FN

GBT Commences Research and Development of Delta, an Automated IC Layout Process Migration and Compaction Technology Other OTC:GTCH

(MENAFN- GlobeNewsWire - Nasdaq) SAN DIEGO, April 15, 2021 (GLOBE NEWSWIRE) -- GBT Technologies Inc. (OTC PINK: GTCH ) ("GBT' or the 'Company'), started research and development of Delta, a new EDA ...