XCENA raises $135M for its computational memory controller

XCENA Inc., a startup with a memory device designed to speed up artificial intelligence clusters, today announced that it has raised $135 million in funding. The Series B round was led by Korean funds ...
Semiconductor Engineering

Setting The Memory Controller Free From Managing DRAM Maintenance Ops (ETH Zurich)

A new technical paper titled “A Case for Self-Managing DRAM Chips: Improving Performance, Efficiency, Reliability, and Security via Autonomous in-DRAM Maintenance Operations” was published by ...
AppleInsider

Why Apple uses integrated memory in Apple Silicon — and why it's both good and bad

Apple's Unified Memory Architecture first brought changes to the Mac with Apple Silicon M1 chips. There are clear architectural benefits for the hardware — and it is both good and bad for consumers.
CNET

Why Intel doesn't include a memory controller on its chips

Michael Kanellos is editor at large at CNET News.com, where he covers hardware, research and development, start-ups and the tech industry overseas. If you want to know why Intel doesn't include a ...
Semiconductor Engineering

Redefining XPU Memory For AI Data Centers Through Custom HBM4: Part 3

This is the third and final of a series from Alphawave Semi on HBM4 and gives and examines custom HBM implementations. Click here for part 1, which gives an overview of the HBM standard, and here for ...