Electronic Design

"Missing Link" Generates HDL Code From Simulink/Matlab Models

A persistent bugaboo in adopting electronic system-level (ESL) design methodologies is how to avoid wasting the work done above RTL. Certainly, designers of DSPs in particular have enjoyed using the ...
Electronic Design

The MathWorks App Generates HDL Code From System Models

The Simulink HDL Coder automatically generates synthesizable hardware description language (HDL) code from models created in the company’s Simulink and Stateflow software. It produces ...
EDN

Product how-to: Achieving STARC and DO-254 compliance using HDL Coder-generated code

HDL Coder generates target independent, synthesizable Verilog and VHDL code from MATLAB functions, Simulink models, and Stateflow charts. The generated HDL code is bit-true and cycle-accurate to ...
New Electronics

MathWorks enhances range with fpga and asic coding and verification products

In a move described as a 'significant enhancement' to its product range, MathWorks has launched HDL Coder, which allows HDL code to be generated directly from MATLAB and used to implement fpgas and ...
EDN

The MathWorks Updates Simulink Control Design With Improved PID Tuning Features

The MathWorks today announced the availability of Simulink Control Design 3.0, equipped with new features that automate the process of tuning proportional-integral-derivative (PID) controllers. These ...
Business Wire

Simulink Code Inspector Strengthens MathWorks Support for DO-178 Certification

NATICK, Mass.--(BUSINESS WIRE)--MathWorks today introduced Simulink Code Inspector, which facilitates the review of source code generated from Simulink models. Aerospace engineers can now use Simulink ...
Business Wire

MathWorks Speeds FPGA and ASIC Verification with Universal Verification Methodology (UVM) Support

NATICK, Mass.--(BUSINESS WIRE)--MathWorks today announced that HDL Verifier provides support for the Universal Verification Methodology (UVM) starting with Release 2019b, which is currently available.