iDenfy combines physical and electronic ID verification in a single onboarding flow

The alternative workflow will require pre-saved electronic ID credentials without the need to enter personal details ...
EDN

“In-design” physical verification is “on-time” physical verification

Physical design engineers who create chips at the 45-nm node and beyond face a difficult task. The time-tested flows used at previous nodes are no longer viable to maintain productivity at today’s ...
EDN

Ultrasparc III Passes Physical Verification

Since 1990, Sun Microsystems has tracked factors affecting design complexity and productivity with an extensive set of indicators. Based on this information, Sun constructed and adopted a methodology ...
Electronic Design

Combine Pattern Matching with DFM to Optimize Layouts

Pattern matching is best known for its use in detecting lithographic hotspots, but it’s also widely used across all physical verification flows, and has expanded into design-for-manufacturing (DFM) ...
Semiconductor Engineering

Interface DRC Can Streamline Chip-Level Interface Physical Verification

In most design companies, the chip-level physical implementation teams responsible for design floorplanning in place and route (P&R) environments also manage top-level physical verification from the ...
Nasdaq

GBT Commences Research Project to Enhance Nanometer ICs Physical Verification Process

SAN DIEGO, Feb. 02, 2021 (GLOBE NEWSWIRE) -- GBT Technologies Inc. (OTC PINK: GTCH) ("GBT” or the “Company”), started a research project, internal name VeriSpeed, to develop new system and methods to ...