New Nvidia AI chip design raises questions over HBM demand: Report

Seoul [South Korea], March 16 (ANI): Nvidia may unveil a new artificial intelligence inference chip architecture built around on-chip static random access memory, or SRAM, at the Nvidia GTC 2026 ...
Electronics Weekly

NanoIC adds SRAM to 2nm PDK

The NanoIC pilot line, a European initiative coordinated by imec for accelerating innovation in process technologies beyond 2nm, has released the N2 P-PDK v1.0, an important update of its N2 ...
Business Wire

SkyWater Announces Availability of SRAM Memory Compiler for 90 nm Strategic Rad Hard by Process Offering

BLOOMINGTON, Minn. & SEATTLE--(BUSINESS WIRE)--SkyWater Technology (NASDAQ: SKYT), the trusted technology realization partner, today announced a new component of its RH90 IP ecosystem to enable 90 nm ...
Semiconductor Engineering

Computational SRAM (C-SRAM) Solution Combining In- and Near-Memory Computing Approaches

New academic paper titled “Towards a Truly Integrated Vector Processing Unit for Memory-bound Applications Based on a Cost-competitive Computational SRAM Design Solution”, from researchers at Univ.
Semiconductor Engineering

Mixed SRAM And eDRAM Cell For Area And Energy-Efficient On-Chip AI Memory (Yale Univ.)

“AI chips commonly employ SRAM memory as buffers for their reliability and speed, which contribute to high performance. However, SRAM is expensive and demands significant area and energy consumption.
Design-Reuse

An Effective SRAM Repair Strategy Based on eMemory NeoFuse OTP and Siemens Tessent™ MemoryBIST

In advanced process nodes, the severe decoupling between SRAM scaling stagnation and logic circuit scaling, combined with the surging on-chip memory demands from Large Language Model (LLM) training ...
Nature

Embedded Dynamic Random Access Memory Design

Embedded Dynamic Random Access Memory (eDRAM) design is rapidly evolving to meet the escalating performance and energy efficiency demands of contemporary processors. This technology has emerged as a ...