Boundry-scan testing (IEEE1149.1/JTAG) is a novel procedure for some test engineers and technicians. But ScanWorks Interconnect Development Station version 3.4 from Asset Intertech should ease their ...
Integrated circuit complexity and integration continuously advances, posing challenges to the development process. Market profitability, however, demands that products be designed and produced as fast ...
Description: Discusses different aspects of VLSI testing and formal verification of designs. Design and manufacturing defect models are introduced along with test generation and fault simulation ...
Return to original Test Digest book review. VLSI Test Principles and Architectures: Design for Testability, Laung-Terng Wang, Chen-Wen Wu, and Xiaoquing Wen (editors), Elsevier Science ...
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