There is a rapidly growing interest in the use of structural techniques for testing random logic. In particular, much has been published on new techniques for on-chip compression of automatic test ...

Automatic test-pattern generation (ATPG) has played a key role in semiconductor logic test, but several trends driving the need for semiconductor test quality are challenging traditional ATPG tools.

Nothing accelerates a testability engineer's receding hairline as the addition of further clock domains to the latest SoC or IC design. Avoiding clock skew during test is becoming one of the biggest ...