Electronic Design

Simplify SoC Development With Embedded Testing

While the use of complex system-on-a-chip (SoC) designs has increased, unfortunately, that hasn't increased the time-to-market window for designers and chip manufacturers. As SoC designs become more ...
EDN

Design holds the key to cost-effective SOC testing

As device complexity grows and fabrication costs continue to fall, test is emerging as the largest expense in complex SOC (system-on-chip) IC manufacturing. At the same time, ICs continue to ...
EDN

‘Wrap’ your cores to enable SoC test

Deep submicron technology enabled the design of the industry's first very large chips. The magnitude of the design effort involved in creating these chips led to the adoption of reuse methodologies ...
Electronic Design

Synopsys Debuts DesignWare STAR Hierarchical System to Accelerate SoC Test

September 11, 2013. Synopsys Inc. has announced the availability of its DesignWare STAR Hierarchical System, an automated hierarchical test solution for efficiently testing SoCs, including ...