EDN

Finding fault with traditional test pattern types

It is well established that transition and stuck-at fault models detect the vast majority of production defects. The transition fault model focuses on detecting timing-related defects. However, the ...
Semiconductor Engineering

Reducing Chip Test Costs With AI-Based Pattern Optimization

The old adage “time is money” is highly applicable to the production testing of semiconductor devices. Every second that a wafer or chip is under test means that the next part cannot yet be tested.
Hackaday

test pattern

[Nicholas Murray]’s Composite Test Pattern Generator is a beautifully-made, palm-sized tool that uses an ESP32-based development board to output different test patterns in PAL/NTSC. If one is checking ...
EDN

Design for test boot camp, part 4: Built-in self-test

Logic built-in self-test (LBIST), is a mechanism that lets an (IC) test the integrity of its own digital logic structures. LBIST operates by stimulating the logic-based operations of the IC and then ...
Electronic Design

Combining Logic BIST and Scan Test Compression

Small geometries have projected IC technology into an era where test has become a crucial part in the chip design process and have introduced new challenges needing solutions that use already ...
Electronic Design

Using Timing Constraints For Generating At-Speed Test Patterns

Handling timing exception paths in ATPG tools while creating at-speed patterns has always been a tough and tricky task. It is well understood that at-speed testing is a requirement for modern ...