Business Wire

MathWorks Speeds FPGA and ASIC Verification with Universal Verification Methodology (UVM) Support

NATICK, Mass.--(BUSINESS WIRE)--MathWorks today announced that HDL Verifier provides support for the Universal Verification Methodology (UVM) starting with Release 2019b, which is currently available.
Business Wire

SpringSoft’s Verdi Debug Software Expands Verification Interoperability with Comprehensive UVM Support

HSINCHU, Taiwan--(BUSINESS WIRE)--SpringSoft, Inc., a global supplier of specialized IC design software, today announced comprehensive support for the Universal Verification Methodology (UVM) with its ...
EDN

A SystemC-based UVM verification infrastructure

My company, TVS, recently completed a SystemC-based Universal Verification Methodology (UVM) project for Blu Wireless Technology, a UK-based company that develops silicon-proven mmWave wireless ...
Yahoo Finance

Breker Verification Systems Unleashes the SystemUVM Initiative to Empower UVM Engineering

SAN JOSE, Calif., Feb. 28, 2022 (GLOBE NEWSWIRE) -- Breker Verification Systems used the opening of DVCon U.S. today to unveil SystemUVM™, a framework designed to simplify specification model ...
Semiconductor Engineering

UVM Do’s And Don’ts For Effective Verification

With more than a year of production use, the Accellera Systems Initiative UVM is now clearly the methodology of choice for verification. The rush to adopt UVM has both matured the BCL quickly, ...
EDN

Improving analog design verification using UVM

As technology becomes more integrated into our everyday life, our chips need to better communicate with the analog world. Most modern system on chip (SoC) designs therefore contain analog and ...
TechRepublic

Design and Development of Verification Environment to Verify GPIO Core using UVM

The GPIO (General Purpose Input/Output) core design provides a general purpose input/output interface to a 32-bit On-chip Peripheral Bus (OPB). This GPIO core requires simple output and/or input ...
New Electronics

Aldec adds UVM Generator to Riviera-PRO

Aldec, a specialist in mixed HDL language simulation and hardware-assisted verification for FPGA, ASIC and SoC designs, has added an automatic UVM Generator function to Riviera-PRO. The addition is ...
Design-Reuse

AMIQ EDA Updates UVM Rule Checks for Latest Release of the Universal Verification Methodology Standard

June 24, 2021, San Jose, California — AMIQ EDA, a pioneer in integrated development environments (IDEs) for hardware design and verification and a provider of platform-independent software tools for ...
Design-Reuse

Design patterns in SystemVerilog OOP for UVM verification

SystemVerilog supports templates for generic code writing using parameterized classes. Here we’re going to describe some of the design patterns in the code that make up the UVM base class library.
Electronic Design

Remove The Processor Dilemma From Constrained-Random Verification

Block-level verification has become a fairly mature technology over the past 10 years. All of the major EDA players support constrained-random stimulus generation in the simulation testbench. As part ...