Hackaday

Xilinx Borrows Code For Their Own Devices

Back in 2012, [tmbinc] discovered a neat little undocumented feature in the Xilinx ISE: the ability to use TCP/IP instead of JTAG cables. [tmbinc] was working on an Open Hardware USB analyzer and ...
Hackaday

FPGA Used VHDL For Fractals

Over on GitHub, [ttsiodras] wanted to learn VHDL. So he started with an algorithm to do Mandelbrot sets and moved it to an FPGA. Because of the speed, he was able to accomplish real-time zooming. You ...
CRN

Xilinx Makes Composable, Easy-To-Code SmartNIC With Alveo SN1000

Xilinx, which is being acquired by AMD for $35 billion, has revealed the Alveo SN1000, the ‘industry’s first’ composable SmartNIC. ‘We’re providing an application-specific acceleration pipeline, where ...
EDN

VHDL simulator flags inadequately tested code

The CoValidator VHDL simulator and coverage analyzer, the first component of Impulse's forthcoming CoDeveloper hardware/software design suite, enables users to quickly identify specific lines of code ...