Electronic Design

Imec Teams With Cadence on DFT Solution for 3-D Memory-on-Logic

January 25, 2013. At the European 3D TSV Summit in Grenoble, France, on January 22-23, 2013, imec announced that together with Cadence Design Systems they have developed, implemented, and validated an ...
EDN

Imec, Cadence develop 3-D memory-on-logic DFT tool

Nanoelectronics research firm Imec and Cadence Design Systems announced at this week’s European 3D TSV Summit in Grenoble, France, the joint development of an automated DFT (design-for-test) solution ...
Electronic Design

Cadence releases XJTAG DFT Assistant for OrCAD Capture

San Jose, CA. Cadence Design Systems has announced that its OrCAD Capture has been enhanced to now include XJTAG DFT Assistant, an easy-to-use interface that increases the design-for-test (DFT) and ...