The need for deterministic latency in converter-based applications. Three subclasses were introduced in JESD2054B to deal with deterministic latency. Implementation methods for subclasses 0, 1, and 2.

The Altera JESD204B IP core is a high-speed point-to-point serial interface for digital-to-analog (DAC) or analog-to-digital (ADC) converters to transfer data to or from the FPGA devices. The JESD204B ...

This file type includes high resolution graphics and schematics. JESD204B is a new 12.5-Gbit/s serial interface standard for high-speed, high-resolution data converters. Already, devices from ...